Electrical over stresses (EOSs) are a constant cause of failure for integrated circuits. According to certain reports, approximately 40% of the failures found in integrated circuits can be attributed to EOS phenomena or events.
In particular, for semiconductor devices, EOS events comprise a wide range of stresses of an electrical nature, due, for example, to electro-magnetic pulses (EMPs), system transients of various nature (the so-called “overvoltage spikes” on the supply lines and input/output lines) and electro-static discharge (ESD). In particular, events belonging to the latter type of EOS have durations of between 1 ns and 1 μs, and occur prevalently in the production and handling stages, i.e., when the device is not subject to electrical biasing.
The failures linked to EOS events in semiconductor devices can be classified according to the respective primary failure mechanism: failures induced as a result of thermal or electrical effects (phenomena of thermomigration or electromigration of material, which involve the metallization layers), phenomena of latch-up, breakdown of the gate oxide, and other failures that can be correlated to electrical fields.
The EOS events considered herein belong to the family of system transients (on the supply lines and input/output lines). For these events, the sensitivity as a function of temperature depends upon the failure mode considered. For example, it is minimal for (thermo-electrical) damage of the metallizations and very serious for breakdown of the oxides.
These particular events can be defined as overvoltage or overcurrent phenomena which have a duration of between 1 μs and 1 ms, and which occur during operation of the device.
“Automation of electrical overstress characterization for semiconductor devices”, Diaz C. H., Hewlett-Packard Journal, Hewlett-Packard Co. Palo Alto Calif., US, vol. 45 no. 5, pages 106-111, describes an automatic test system developed to characterize semiconductor devices and interconnect failures caused by electrical overstress. Electrical stress in the form of current pulses of increasing amplitude is applied to a device under test in the testing mode. The test system was developed for monitoring EOS robustness in advanced CMOS processors under test.
“EOS/EDS; ADI Reliability Handbook”, 2000 Analog Devices Inc. Norwood, Mass. 02062, pages 1-22, describes Human Body Model and Machine Model test methods that simulates the application of EOS on ICs.
US 2007/0018670 A1 describes a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch. The control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and the circuit is integrated into the DUT. The system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.
“Improvement of degradation detection in ESD test for semiconductor device”, Satoh S ED—Institute of Electrical and Electronics Engineers, conference record of the 2002 IEEE Industry applications conference 37th IAS annual meeting, Pittsburgh, Pa., Oct. 13-18, 2002 describes ESD test as evaluation tests for semiconductor products. In particular, the most popular and standardized test is the Human Body Model ESD test. In HBM ESD test some issues are experienced in the detection of device degradation as pass/fail judgment after ESD stress applied. Some kind of device degradation cannot be detected with the conventional test condition and criteria. Improved judgment test using effective combination of optimized DC leak test and device functional test was proposed.
US 2005/017745 A1 describes an electrostatic withstand voltage test method that enables semiconductor integrated circuit testing to be performed with a high degree of precision and at low cost. In this method, with one of ground pins VSS and VSSI of a semiconductor integrated circuit grounded, static electricity is applied from a static electricity discharge apparatus to all pins of semiconductor integrated circuit, after which, with power supply apparatus connected to power supply pin VDD of semiconductor integrated circuit and the other grounded, a leakage current test apparatus is connected to all signal pins and pin leakage current is tested, and with ground pin VSSI of the internal circuitry of semiconductor integrated circuit grounded and leakage current test apparatus connected to power supply pin VDDI, a pattern generator that supplies a digital signal is connected to signal input pins (IN, I/O), and power supply leakage current is tested.
U.S. Pat. No. 5,132,612 describes an apparatus for applying high current fast rise time pulses simulating electrostatic discharge (ESD) to various combinations of pins of a device under test (e.g., a microcircuit). The apparatus also provides for testing of the DUT after the performance of ESD stress testing. The apparatus establishes electrical connections between the terminals of a high voltage pulse generator (HVPG) and several different combinations of the DUT pins in sequence in order to apply ESD stresses. The apparatus further provides functional parameter tests whether the connection to the DUT pins during ESD stressing has caused the DUT to fail.
Further advances in testing the performance of electronic devices in the presence of electrical overstresses are, however, needed.